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functional block diagram - utopia level 2 mode rxclk clock/data recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 0 rx 0 clock/data recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 1 rx 1 clock/data recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 2 rx 2 phy-atm interface (utopia or dpi) microprocessor (utility bus) interface txdata[15:0] txclk rxdata[15:0] 3 3 rxled[2:0] txled[2:0] txaddr[4:0] rxaddr[4:0] + + + + txsoc txclav txparity mode[1:0] rxsoc rxclav rxparity 4781 drw 01 + + ale ad[7:0] osc driver driver driver integrated device technology, inc. ? commercial and industrial temperature ranges november 1998 ?1998 integrated device technology, inc. dsc-4781/1 1 triple port phy (physical layer) for 25.6 and 51.2 mbps atm networks preliminary IDT77V1253 features ? performs the phy-transmission convergence (tc) and physical media dependent (pmd) sublayer functions for three 25.6 mbps atm channels ? compliant to atm forum (af-phy-040.000) and itu-t i.432.5 specifications for 25.6 mbps physical interface ? also operates at 51.2mbps ? utopia level 1, utopia level 2, or dpi-4 interface ? 3-cell transmit & receive fifos ? led interface for status signalling ? supports utp category 3 physical media ? interfaces to standard magnetics ? low-power cmos ? 3.3v supply with 5v tolerant inputs ? 144-pin pqfp package (28 x 28 mm) description the IDT77V1253 is a member of idt's family of products supporting asynchronous transfer mode (atm) data commu- nications and networking. the IDT77V1253 implements the physical layer for 25.6 mbps atm, connecting three serial copper links (utp category 3) to one atm layer device such as a sar or a switch asic. the IDT77V1253 also operates at 51.2 mbps, and is well suited to backplane driving applica- tions. the 77v1253-to-atm layer interface is selectable as one of three options: 16-bit utopia level 2, 8-bit utopia level 1 multi-phy, or triple 4-bit dpi (data path interface). the IDT77V1253 is fabricated using idt's state-of-the-art cmos technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of cmos. the idt logo is a registered trademark of integrated device technology, inc.
2 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 1. pin assignments vdd gnd tx0- tx0+ vdd mm mode1 mode0 gnd dnc txled2 txled1 txled0 vdd txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 txdata8 txdata9 txdata10 txdata11 txdata12 txdata13 txdata14 txdata15 txparity txsoc txaddr4 txaddr3 vdd txaddr2 txaddr1 txaddr0 txclav txclk gnd vdd rxclk rxaddr0 rxaddr1 gnd rxaddr2 rxaddr3 rxaddr4 rxclav rxsoc gnd vdd rxparity rxdata15 rxdata14 rxdata13 rxdata12 rxdata11 rxdata10 rxdata9 rxdata8 gnd vdd rxdata7 rxdata6 rxdata5 rxdata4 vdd gnd dnc dnc vdd da se ad7 ad6 ad5 ad4 gnd ad3 ad2 ad1 ad0 vdd ale gnd vdd gnd dnc rxled2 rxled1 rxled0 vdd gnd rxdata0 rxdata1 rxdata2 rxdata3 osc tx1+ tx1- gnd agnd avdd mb ma rx0+ rx0- avdd agnd agnd avdd rx1+ rx1- avdd agnd agnd avdd agnd avdd agnd agnd avdd rx2+ rx2- avdd agnd agnd avdd avdd agnd gnd tx2+ tx2- 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 77v1253 144-pqfp 4781 drw 02
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 3 line side signals signal name pin number i/o signal description rx0+, - 139, 138 in port 0 positive and negative receive differential input pair rx1+, - 133, 132 in port 1 positive and negative receive differential input pair rx2+, - 121, 120 in port 2 positive and negative receive differential input pair tx0+, - 4, 3 out port 0 positive and negative transmit differential output pair tx1+, - 144, 143 out port 1 positive and negative transmit differential output pair tx2+, - 110, 109 out port 2 positive and negative transmit differential output pair utility bus signals signal name pin number i/o signal description ad[7:0] 101, 100, 99, 98 in/out utility bus address/data bus. the address input is sampled on 96, 95, 94, 93 the falling edge of ale. data is output on this bus when a read is performed. input data is sampled at the completion of a write operation. ale 91 in utility bus address latch enable. asynchronous input. an address on the ad bus is sampled on the falling edge of ale. ale may be either high low when the ad bus is being used for data. cs 90 in utility bus asynchronous chip select. cs must be asserted to read or write an internal register. it may remain asserted at all times if desired. rd 89 in utility bus read enable. active low asynchronous input. after latching an address, a read is performed by deasserting wr and asserting rd and cs . wr 88 in utility bus write enable. active low asynchronous input. after latching an address, a write is performed by deasserting rd , placing data on the ad bus, and asserting wr and cs . data is sampled when wr or cs is deasserted. miscellaneous signals signal name pin number i/o signal description da 103 in reserved signal. this input must be connected to logic low. dnc 12, 82, 105, 106 out do not connect. do not connect these pins to anything external to the chip. they must remain open. int 85 out interrupt. int is an open-drain output, driven low to indicate an open drain interrupt. once low, int remains low until the interrupt status in the appropriate interrupt status register is read. interrupt sources are programmable via the interrupt mask registers. ma 114 in reserved signal. this input must be connected to logic low. mb 115 in reserved signal. this input must be connected to logic low. mm 6 in reserved signal. this input must be connected to logic high. mode[1:0] 7, 8 in mode selects. they determine the configuration of the phy/atm interface. 00 = utopia level 2. 01 = utopia level 1. 10 = dpi. 11 is reserved. osc 126 in ttl line rate clock source, driven by a 100 ppm oscillator. 32 mhz for 25.6 mbps; 64 mhz for 51.2 mbps. rst 87 in reset. active low asynchronous input resets all control logic, counters and fifos. a reset must be performed after power up prior to normal operation of the part. rxled[2:0] 81, 80, 79 out receive led drivers. driven low for 2 23 rclk or dpiclk cycles, beginning with rxsoc when that port receives a good (non-null and non-errored) cell. drives 8 ma both high and low. one per port. table 1. signal descriptions
4 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges rxref 9 out receive reference. active low, synchronous to osc. rxref pulses low for a programmable number of clock cycles when an x_8 command byte is received. register 0x40 is programmed to indicate which port is referenced. se 102 in reserved signal. this input must be connected to logic low. txled[2:0] 13, 14, 15 out ports 2 thru 0 transmit led driver. goes low for 2 23 tclk or dpiclk cycles, beginning with txsoc when this port receives a cell for transmission. 8ma drive current both high and low. one per port. txref 10 in transmit reference. synchronous to osc. when this pin is asserted, an x_8 command byte is inserted into the transmit data stream. logic for this signal is programmed in register 0x40. typical application is wan timing. power supply signals signal name pin number i/o signal description agnd 112, 117, 118, - analog ground. agnd supply a ground reference to the analog 123,124,127, portion of the chip, which sources a more constant current 129,130,135, than the digital portion. 136, 141 avdd 113, 116, 119, - analog power supply. 3.3 0.3v avdd supply power to the 122, 125, 128, analog portion of the chip, which draws a more constant 131, 134, 137, current than the digital portion. 140 gnd 2, 11, 44, 50, 56 - digital ground 67, 77, 83, 86, 97, 107, 111, 142 vdd 1, 5, 16, 38, 45 - digital power supply. 3.3 0.3v 57, 68, 78, 84, 92, 104, 108 16-bit utopia 2 signals (mode[1:0] = 00) signal name pin number i/o signal description rxaddr[4:0] 53, 52, 51, 49, 48 in utopia 2 receive address bus. this bus is used in polling and selecting the receive port. the port addresses are defined in bits [4:0] of the enhanced control registers. rxclav 54 out utopia 2 receive cell available. indicates the cell available status of the addressed port. it is asserted when a full cell is available for retrieval from the receive fifo. when none of the three ports is addressed, rxclav is high impedance. rxclk 46 in utopia 2 receive clock. this is a free running clock input. rxdata[15:0] 59, 60, 61, 62, out utopia 2 receive data. when one of the three ports is selected, the 63, 64, 65, 66, 77v1253 transfers received cells to an atm device across this bus. 69, 70, 71, 72, also see rxparity. 73, 74, 75, 76 rxen 47 in utopia 2 receive enable. driven by an atm device to indicate its ability to receive data across the rxdata bus. rxparity 58 out utopia 2 receive data parity. odd parity over rxdata[15:0]. rxsoc 55 out utopia 2 receive start of cell. asserted coincident with the first word of data for each cell on rxdata. txaddr[4:0] 36, 37, 39, 40, 41 in utopia 2 transmit address bus. this bus is used in polling and selecting the transmit port. the port addresses are defined in bits [4:0] of the enhanced control registers. txclav 42 out utopia 2 transmit cell available. indicates the availability of room in the transmit fifo of the addressed port for a full cell. when none of the three ports is addressed, txclav is high impedance. signal name pin number i/o signal description table 1. signal descriptions (continued)
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 5 txclk 43 in utopia 2 transmit clock. this is a free running clock input. txdata[15:0] 32, 31, 30, 29, in utopia 2 transmit data. an atm device transfers cells across this 28, 27, 26, 25, bus to the 77v1253 for transmission. also see txparity. 24, 23, 22, 21, 20, 19, 18, 17 txen 34 in utopia 2 transmit enable. driven by an atm device to indicate it is transmitting data across the txdata bus. txparity 33 in utopia 2 transmit data parity. odd parity across txdata[15:0]. parity is checked and errors are indicated in the interrupt status registers, as enabled in the master control registers. no other action is taken in the event of an error. tie high or low if unused. txsoc 35 in utopia 2 transmit start of cell. asserted coincident with the first word of data for each cell on txdata. 8-bit utopia level 1 signals (mode[1:0] = 01) signal name pin number i/o signal description rxclav[2:0] 65, 66, 54 out utopia 1 receive cell available. indicates the cell available status of the respective port. it is asserted when a full cell is available for retrieval from the receive fifo. rxclk 46 in utopia 1 receive clock. this is a free running clock input. rxdata[7:0] 69, 70, 71, 72, out utopia 1 receive data. when one of the three ports is selected, the 73, 74, 75, 76 77v1253 transfers received cells to an atm device across this bus. bit 5 in the diagnostic control registers determines whether rxdata tri-states when rxen [2:0] are high. also see rxparity. rxen [2:0] 49, 48, 47 in utopia 1 receive enable. driven by an atm device to indicate its ability to receive data across the rxdata bus. one for each port. rxparity 58 out utopia 1 receive data parity. odd parity over rxdata[7:0]. rxsoc 55 out utopia 1 receive start of cell. asserted coincident with the first word of data for each cell on rxdata. tri-statable as determined by bit 5 in the diagnostic control registers. txclav[2:0] 40, 41, 42 out utopia 1 transmit cell available. indicates the availability of room in the transmit fifo of the respective port for a full cell. txclk 43 in utopia 1 transmit clock. this is a free running clock input. txdata[7:0] 24, 23, 22, 21, in utopia 1 transmit data. an atm device transfers cells across this 20, 19, 18, 17 bus to the 77v1253 for transmission. also see txparity. txen [2:0] 26, 25, 34 in utopia 1 transmit enable. driven by an atm device to indicate it is transmitting data across the txdata bus. one for each port. txparity 33 in utopia 1 transmit data parity. odd parity across txdata[7:0]. parity is checked and errors are indicated in the interrupt status registers, as enabled in the master control registers. no other action is taken in the event of an error. tie high or low if unused. txsoc 35 in utopia 1 transmit start of cell. asserted coincident with the first word of data for each cell on txdata. dpi mode signals (mode[1:0] = 10) signal name pin number i/o signal description dpiclk 43 in dpi source clock for transmit. this is the free-running clock used as the source to generate pn_tclk. pn_rclk 51, 49, 48 in dpi port 'n' receive clock. pn_rclk is cycled to indicate that the interfacing device is ready to receive a nibble of data on pn_rd[3:0] of port 'n'. pn_rd[3:0] 63, 64, 65, 66, out dpi port 'n' receive data. cells received on port 'n' are passed to 69, 70, 71, 72, the interfacing device across this bus. each port has its own 73, 74, 75, 76 dedicated bus. table 1. signal descriptions (continued) signal name pin number i/o signal description
6 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges table 2. signal assignment as a function of phy/atm interface mode signal name pin number 16-bit utopia 2 8-bit utopia 1 dpi mode[1,0] = 00 mode[1,0] = 01 mode[1,0] = 10 vdd 1 gnd 2 tx0- 3 tx0+ 4 vdd 5 mm 6 mode1 7 mode0 8 rxref 9 txref 10 gnd 11 dnc 12 txled2 13 txled1 14 txled0 15 vdd 16 txdata0 17 txdata0 txdata0 p0_td[0] txdata1 18 txdata1 txdata1 p0_td[1] txdata2 19 txdata2 txdata2 p0_td[2] txdata3 20 txdata3 txdata3 p0_td[3] txdata4 21 txdata4 txdata4 p1_td[0] txdata5 22 txdata5 txdata5 p1_td[1] txdata6 23 txdata6 txdata6 p1_td[2] txdata7 24 txdata7 txdata7 p1_td[3] txdata8 25 txdata8 txen[1] p2_td[0] txdata9 26 txdata9 txen[2] p2_td[1] txdata10 27 txdata10 see note 2 p2_td[2] txdata11 28 txdata11 see note 2 p2_td[3] txdata12 29 txdata12 see note 2 see note 2 pn_rfrm 58, 54, 55 out dpi port 'n' receive frame. pn_rfrm is asserted for one cycle immediately preceding the transfer of each cell on pn_rd[3:0]. pn_tclk 39, 40, 41 out dpi port 'n' transmit clock. pn_tclk is derived from dpiclk, and is cycled when the respective port is ready to accept another 4 bits of data on pn_td[3:0]. pn_td[3:0] 28, 27, 26, 25, in dpi port 'n' transmit data. cells are passed across this bus to the 24, 23, 22, 21, phy for transmission on port 'n'. each port has its own dedicated 20, 19, 18, 17 bus. pn_tfrm 36, 33, 34, 35 in dpi port 'n' transmit frame. start of cell signal which is asserted for one cycle immediately preceding the first 4 bits of each cell on pn_td[3:0]. table 1. signal descriptions (continued) signal name pin number i/o signal description
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 7 table 2. signal assignment as a function of phy/atm interface mode (cont.) signal name pin mumber 16-bit utopia 2 8-bit utopia 1 dpi txdata13 30 txdata13 see note 2 see note 2 txdata14 31 txdata14 see note 2 see note 2 txdata15 32 txdata15 see note 2 see note 2 txparity 33 txparity txparity p2_tfrm txen 34 txen txen[0] p1_tfrm txsoc 35 txsoc txsoc p0_tfrm txaddr4 36 txaddr4 see note 2 see note 2 txaddr3 37 txaddr3 see note 2 see note 2 vdd 38 txaddr2 39 txaddr2 see note 1 p2_tclk txaddr1 40 txaddr1 txclav[2] p1_tclk txaddr0 41 txaddr0 txclav[1] p0_tclk txclav 42 txclav txclav[0] see note 1 txclk 43 txclk txclk dpiclk gnd 44 vdd 45 rxclk 46 rxclk rxclk see note 2 rxen 47 rxen rxen[0] see note 2 rxaddr0 48 rxaddr0 rxen[1] p0_rclk rxaddr1 49 rxaddr1 rxen[2] p1_rclk gnd 50 rxaddr2 51 rxaddr2 see note 2 p2_rclk rxaddr3 52 rxaddr3 see note 2 see note 2 rxaddr4 53 rxaddr4 see note 2 see note 2 rxclav 54 rxclav rxclav[0] p1_rfrm rxsoc 55 rxsoc rxsoc p0_rfrm gnd 56 vdd 57 rxparity 58 rxparity rxparity p2_rfrm rxdata15 59 rxdata15 see note 1 see note 1 rxdata14 60 rxdata14 see note 1 see note 1 rxdata13 61 rxdata13 see note 1 see note 1 rxdata12 62 rxdata12 see note 1 see note 1 rxdata11 63 rxdata11 see note 1 p2_rd[3] rxdata10 64 rxdata10 see note 1 p2_rd[2] rxdata9 65 rxdata9 rxclav[2] p2_rd[1] rxdata8 66 rxdata8 rxclav[1] p2_rd[0] gnd 67 vdd 68 rxdata7 69 rxdata7 rxdata7 p1_rd[3] rxdata6 70 rxdata6 rxdata6 p1_rd[2] rxdata5 71 rxdata5 rxdata5 p1_rd[1] rxdata4 72 rxdata4 rxdata4 p1_rd[0] rxdata3 73 rxdata3 rxdata3 p0_rd[3] rxdata2 74 rxdata2 rxdata2 p0_rd[2] rxdata1 75 rxdata1 rxdata1 p0_rd[1]
8 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges rxdata0 76 rxdata0 rxdata0 p0_rd[0] gnd 77 vdd 78 rxled0 79 rxled1 80 rxled2 81 dnc 82 gnd 83 vdd 84 int 85 gnd 86 rst 87 wr 88 rd 89 cs 90 ale 91 vdd 92 ad0 93 ad0 94 ad0 95 ad0 96 gnd 97 ad0 98 ad0 99 ad0 100 ad0 101 se 102 da 103 vdd 104 dnc 105 dnc 106 gnd 107 vdd 108 tx2- 109 tx2+ 110 gnd 111 agnd 112 avdd 113 ma 114 mb 115 avdd 116 agnd 117 agnd 118 avdd 119 rx2- 120 rx2+ 121 table 2. signal assignment as a function of phy/atm interface mode (cont.) signal name pin mumber 16-bit utopia 2 8-bit utopia 1 dpi
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 9 avdd 122 agnd 123 agnd 124 avdd 125 osc 126 agnd 127 avdd 128 agnd 129 agnd 130 avdd 131 rx1- 132 rx1+ 133 avdd 134 agnd 135 agnd 136 avdd 137 rx0- 138 rx0+ 139 avdd 140 agnd 141 gnd 142 tx1- 143 tx1+ 144 notes: 1. this output signal is unused in this mode. it must be left unconnected. 2. this input signal is unused in this mode. it must be connected to either logic high or logic low. table 2. signal assignment as a function of phy/atm interface mode (cont.) signal name pin mumber 16-bit utopia 2 8-bit utopia 1 dpi
10 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges rxclk clock/data recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 0 rx port 0 driver 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 1 rx port 1 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 2 rx port 2 utopia multi-phy interface microprocessor (utility bus) interface txdata[7:0] txclk [2:0] rxdata[7:0] [2:0] ale ad[7:0] 3 3 rxled[2:0] txled[2:0] + + + + txsoc txclav[2:0] txparity mode[1:0] rxsoc rxclav[2:0] rxparity 4781 drw 03 + + osc clock/data recovery driver clock/data recovery driver figure 2. block diagram for utopia level 1 configuration (mode[1:0] = 01) 77v1253 overview the 77v1253 is a three-port implementation of the physical layer standard for 25.6mbps atm network communications as defined by atm forum document af-phy-040.000 and itu- t i.432.5. the physical layer is divided into a physical media dependent sub layer (pmd) and transmission convergence (tc) sub layer. the pmd sub layer includes the functions for the transmitter, receiver and clock recovery for operation across 100 meters of category 3 unshielded twisted pair (utp) cable. this is referred to as the line side interface. the tc sub layer defines the line coding, scrambling, data framing and synchronization. on the other side, the 77v1253 interfaces to an atm layer device (such as a switch core or sar). this cell level interface is configurable as either 8-bit utopia level 1 multi-phy, 16-bit utopia level 2, or as three 4-bit dpi interfaces, as determined by two mode pins. this is referred to as the phy-atm interface. the pinout and front page block diagram are based on the utopia 2 configuration. table 2 shows the correspond- ing pin functions for the other two modes, and figures 2 and 3 show functional block diagrams. the 77v1253 is based on the 77105, and maintains signifi- cant register compatibility with it. the 77v1253, however, has additional register features, and also duplicates most of its registers to provide significant independence between the three ports. access to these status and control registers is through the utility bus. this is an 8-bit muxed address and data bus, controlled by a conventional asynchronous read/write hand- shake. additional pins permit insertion and extraction of an 8 khz timing marker, and provide led indication of receive and transmit status. operation at 51.2 mbps in addition to operation at the standard rate of 25.6 mbps, the 77v1253 is also specified to operate at 51.2 mbps. except for the doubled bit rate, all other aspects of operation are identical to the 25.6 mbps mode. the data rate is determined by the frequency of the clock applied to the osc input. osc is 32 mhz for the 25.6 mbps line rate, and 64 mhz for the 51.2 mbps line rate. all ports operate at the same frequency. see page 30 for recommended line magnetics. magnetics for 51.2 mbps operation have a higher bandwidth than mag- netics optimized for 25.6 mbps.
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 11 clock/data recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 0 rx port 0 driver 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 1 rx port 1 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 2 rx port 2 microprocessor (utility bus) interface p0_tfrm 3 3 rxled[2:0] txled[2:0] + + + + p0_rd[3:0] p0_tclk mode[1:0] 4781 drw 04 + + p0_rfrm p0_rclk p0_td[3:0] ale ad[7:0] dpiclk osc p1_tfrm p1_rd[3:0] p1_tclk p1_rfrm p1_rclk p1_td[3:0] p2_tfrm p2_rd[3:0] p2_tclk p2_rfrm p2_rclk p2_td[3:0] dpi multi-phy interface clock/data recovery driver driver clock/data recovery figure 3. block diagram for dpi configuration (mode[1:0] = 10)
12 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 4. tc transmit block diagram functional block diagram (continued) functional description transmission convergence (tc) sub layer introduction the tc sub layer defines the line coding, scrambling, data framing and synchronization. under control of a switch interface or segmentation and reassembly (sar) unit, the 25.6mbps atm phy accepts a 53-byte atm cell, scrambles the data, appends a command byte to the beginning of the cell, and encodes the entire 53 bytes before transmission. these data transformations ensure that the signal is evenly distrib- uted across the frequency spectrum. in addition, the serial- ized bit stream is nrzi coded. an 8 khz timing sync pulse may be used for isochronous communications. data structure and framing each 53-byte atm cell is preceded with a command byte. this byte is distinguished by an escape symbol followed by one of 17 encoded symbols. together, this byte forms one of seventeen possible command bytes. three command bytes are defined: 1. x_x (read: 'escape' symbol followed by another 'es- cape'): start-of-cell with scrambler/descrambler reset. 2. x_4 ('escape' followed by '4'): start-of-cell without scrambler/descrambler reset. 3. x_8 ('escape' followed by '8'): 8khz timing marker. this command byte is generated when the 8khz sync pulse is detected, and has priority over all line activity (data or command bytes). it is transmitted immediately when the sync pulse is detected. when this occurs during a cell transmission, the data transfer is temporarily interrupted on an octet boundary, and the x_8 command byte is inserted. this condition is the only allowed interrupt in an otherwise contiguous transfer. below is an illustration of the cell structure and command byte usage: {x_x} {53-byte atm cell} {x_4} {53-byte atm {x_8} cell} ... in the above example, the first atm cell is preceded by the x_x start-of-cell command byte which resets both the trans- mitter-scrambler and receiver-descrambler pseudo-random nibble generators (prng) to their initial states. the following cell illustrates the insertion of a start-of-cell command without scrambler/descrambler reset. during this cell's transmission, an 8khz timing sync pulse triggers insertion of the x_8 8khz timing marker command byte. phy-atm interface control, hec gen. & insertion scrambler 4 command byte insertion 4 prng 4 scramble nibble next 4b/5b encoding 4 nrzi encoding 1 tx + tx - 32mhz clock input (8khz) 3505 drw 05 3 cells start of cell utopia or dpi interface
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 13 data 0000 0100 1000 1100 symbol 10101 00111 10010 10111 symbol 01001 01101 11001 11101 data 0001 0101 1001 1101 symbol 01010 01110 11010 11110 data 0010 0110 1010 1110 symbol 01011 01111 11011 11111 data 0011 0111 1011 1111 esc(x) = 00010 3217 tbl 01 transmission description refer to figure 4 on the previous page. cell transmission begins with the phy-atm interface. an atm layer device transfers a cell into the 77v1253 across the utopia or dpi transmit bus. this cell enters a 3-cell deep transmit fifo. once a complete cell is in the fifo, transmission begins by passing the cell, four bits (msb first) at a time to the 'scram- bler'. the 'scrambler' takes each nibble of data and exclusive- ors them against the 4 high order bits (x(t), x(t-1), x(t-2), x(t- 3)) of a 10 bit pseudo-random nibble generator (prng). its function is to provide the appropriate frequency distribution for the signal across the line. the prng is clocked every time a nibble is processed, regardless of whether the processed nibble is part of a data or command byte. note however that only data nibbles are scrambled. the entire command byte (x _c) is not scrambled before it's encoded (see diagram for illustration). the prng is based upon the following polynomial: x 10 + x 7 + 1 with this polynomial, the four output data bits (d3, d2, d1, d0) will be generated from the following equations: d3 = d3 xor x(t-3) d2 = d2 xor x(t-2) d1 = d1 xor x(t-1) d0 = d0 xor x(t) the following nibble is scrambled with x(t+4), x(t+3), x(t+2), and x(t+1). a scrambler lock between the transmitter and receiver occurs each time an x_x command is sent. an x_x command is initiated only at the beginning of a cell transfer after the prng has cycled through all of its states (2 10 - 1 = 1023 states). the first valid atm data cell transmitted after power on will also be accompanied with an x_x command byte. each time an x_x command byte is sent, the first nibble after the last escape (x) nibble is xor'd with 1111b (prng = 3ffx). because a timing marker command (x_8) may occur at any time, the possibility of a reset prng start-of-cell command and a timing marker command occurring consecutively does exist (e.g. x_x_x_8). in this case, the detection of the last two consecutive escape (x) nibbles will cause the prng to reset to its initial 3ffx state. therefore, the prng is clocked only after the first nibble of the second consecutive escape pair. once the data nibbles have been scrambled using the prng, the nibbles are further encoded using a 4b/5b process. the 4b/5b scheme ensures that an appropriate number of signal transitions occur on the line. a total of seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles and the one escape (x) nibble. the table below lists the 4-bit data with their corresponding 5-bit symbols: this encode/decode implementation has several very de- sirable properties. among them is the fact that the output data bits can be represented by a set of relatively simple symbols; ? run length is limited to <= 5; ? disparity never exceeds +/- 1. on the receiver, the decoder determines from the received symbols whether a timing marker command (x_8) or a start- of-cell command was sent (x_x or x_4). if a start-of-cell command is detected, the next 53 bytes received are decoded and forwarded to the descrambler. (see tc receive block diagram, figure 4). the output of the 4b/5b encoder provides serial data to the nrzi encoder. the nrzi code transitions the wire voltage each time a '1' bit is sent. this, together with the previous encoding schemes guarantees that long run lengths of either '0' or '1's are prevented. each symbol is shifted out with its most significant bit sent first. when no cells are available to transmit, the 77v1253 keeps the line active by continuing to transmit valid symbols. but it does not transmit another start-of-cell command until it has another cell for transmission. the 77v1253 never generates idle cells. transmit hec byte calculation/insertion byte #5 of each atm cell, the hec (header error control) is calculated automatically across the first 4 bytes of the cell header, depending upon the setting of bit 5 of registers 0x03, 0x13 and 0x23. this byte is then either inserted as a replace- ment of the fifth byte transferred to the phy by the external system, or the cell is transmitted as received. a third operating mode provides for insertion of "bad" hec codes which may aid in communication diagnostics. these modes are con- trolled by the led driver and hec status/control registers.
14 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges atm cell format bit 7 bit 0 bit 7 bit 0 header byte 1 udf header byte 2 payload byte 1 header byte 3 header byte 4 payload byte 48 udf = user defined field (or hec) figure 5. tc receive block diagram functional block diagram (continued) receiver description the receiver side of the tc sublayer operates like the transmitter, but in reverse. the data is nrzi decoded before each symbol is reassembled. the symbols are then sent to the 5b/4b decoder, followed by the command byte interpreter, de-scrambler, and finally through a fifo to the utopia or dpi interface to an atm layer device. note that although the IDT77V1253 can detect symbol and hec errors, it does not attempt to correct them. upon reset or the re-connect, each port's receiver is typi- cally not symbol-synchronized. when not symbol-synchro- 4 phy-atm interface control - recv 4 5 nrzi decoding rx + rx 4 4 prng scramble nibble next reset 32.0mhz clock synthesizer & pll 5b/4b decoding command byte detection, removal, & decode de- scrambler 3505 drw 06 osc 3 cells start of cell utopia or dpi interface nized, the receiver will indicate a significant number of bad symbols, and will deassert the good signal bit as described below. synchronization is established immediately once that port receives an escape symbol, usually as part of the start- of-cell command byte preceding the first received cell. the IDT77V1253 monitors line conditions and can provide an interrupt if the line is deemed 'bad'. the interrupt status registers (registers 0x01, 0x11 and 0x21) contain a good signal bit (bit 6, set to 0 = bad signal initially) which shows the status of the line per the following algorithm: to declare 'good signal' (from "bad" to "good"): there is an up-down counter that counts from 7 to 0 and is initially set to 7. when the clock ticks for 1,024 cycles (32mhz clock, 1,024 cycles = 204.8 symbols) and no "bad symbol" has been received, the counter decreases by one. however, if at least one "bad symbol" is detected during these 1,024 clocks, the counter is increased by one, to a maximum of 7. the good signal bit is set to 1 when this counter reaches 0. the good signal bit could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad symbols have been received.
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 15 IDT77V1253 rxref#0 (x_8 received) txref#0 (x_8 generator) txref#1 (x_8 generator) 4781 drw 07 output mux ltsel#0 rxref#1 (x_8 received) mux rxref#2 (x_8 received) mux ltsel#1 ltsel#2 txref#2 (x_8 generator) rxrefsel[1:0] rxref select decoder input ( reg 40, bit 0) ( reg 40, bit 1) ( reg 40, bit 2) to declare 'bad signal' (from "good" to "bad"): the same up-down counter counts from 0 to 7 (being at 0 to provide a "good" status). when the clock ticks for 1,024 cycles (32mhz clock, 1,024 cycles = 204.8 sym- bols) and there is at least one "bad symbol", the counter increases by one. if it detects all "good symbols" and no "bad symbols" in the next time period, the counter decreases by one. the "bad signal" is declared when the counter reaches 7. the good signal bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at least one "bad symbol" is detected in each of seven consecu- tive groups of 204.8 symbols. figure 6. rxref rxref rxref rxref rxref and txref txref txref txref txref block diagram 8khz timing marker the 8khz timing marker, described earlier, is a completely optional feature which is essential for some applications requiring synchronization for voice or video, and unnecessary for other applications. figure 6 shows the options available for generating and receiving the 8khz timing marker. the source of the marker is programmable in the rxref and txref control register (0x40). each port is individually programmable to either a local source or a looped remote source. the local source is txref , which is an 8khz clock of virtually any duty cycle. when unused, txref should be tied high. also note that it is not limited to 8khz, should a different frequency be desired. when looped, a received x_8 com- mand byte causes one to be generated on the transmit side. a received x_8 command byte causes the 77v1253 to issue a negative pulse on rxref . the source channel of the marker is programmable.
16 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges phy-atm interface the 77v1253 phy offers three choices in interfacing to atm layer devices such as segmentation and reassembly (sar) and switching chips. mode[1:0] are used to select the configuration of this interface, as shown in the table below. mode[1:0] phy-atm interface configuration 00 one 16-bit utopia level 2 port 01 one 8-bit utopia level 1 (multi-phy)port 10 three 4-bit data path interface (dpi) ports utopia is a physical layer to atm layer interface standardized by the atm forum. it has separate transmit and receive channels and specific handshaking protocols. utopia level 2 has dedicated address signals for both the transmit and receive directions that allow the atm layer device to specify with which of the four phy channels it is communicating. utopia level 1 does not have address signals. instead, key handshaking signals are duplicated so that each channel has its own signals. in both versions of utopia, all channels share a single transmit data bus and a single receive data bus for data transfer. dpi is a low-pincount physical layer to atm layer interface. the low-pincount characteristic allows the 77v1253 to incorporate three separate dpi 4-bit ports, one for each of the three serial ports. as with the utopia interfaces, the transmit and receive directions have their own data paths and handshaking. utopia level 2 interface option the 16-bit utopia level 2 interface operates as defined in atm forum document af-phy-0039. this phy-atm interface is selected by setting the mode[1:0] pins both low. this mode is configured as a single 16-bit data bus in the transmit (atm-to-phy) direction, and a single 16-bit data bus in the receive (phy-to-atm) direction. in addition to the data bus, each direction also includes a single optional parity bit, an address bus, and several handshaking signals. the utopia address of each channel is determined by bits 4 to 0 in the enhanced control registers. please note that the transmit bus and the receive bus operate completely independently. the utopia 2 signals are summarized below: txdata[15:0] atm to phy txparity atm to phy txsoc atm to phy txaddr[4:0] atm to phy txen atm to phy txclav phy to atm txclk atm to phy rxdata[15:0] phy to atm rxparity phy to atm rxsoc phy to atm rxaddr[4:0] atm to phy rxen atm to phy rxclav phy to atm header byte 1 header byte 3 header byte 5 payload byte 1 payload byte 3 payload byte 5 payload byte 45 header byte 2 header byte 4 stuff byte payload byte 2 payload byte 4 payload byte 6 payload byte 46 payload byte 47 payload byte 48 bit 15 bit 0 3505 drw 08 first last rxclk atm to phy the atm device starts by polling the phy ports on the utopia 2 bus to determine if any of them has room to accept a cell for transmission (txclav), or has a receive cell available to pass on to the atm device (rxclav). to poll, the atm device drives an address (txaddr or rxaddr) then observes txclav or rxclav on the next cycle of txclk or rxclk. a port must tri-state txclav and rxclav except when it is addressed. if txclav or rxclav is asserted, the atm device may select that port, then transfer a cell to or from it. selection of a port is performed by driving the address of the desired port while txen or rxen is high, then driving txen or rxen low. when txen is driven low, txsoc (start of cell) is driven high to indicate that the first 16 bits of the cell are being driven on txdata. the atm device may chose to temporarily suspend transfer of the cell by deasserting txen . otherwise, txen remains asserted as the next 16 bits are driven onto txdata with each cycle of txclk. in the receive direction, the atm device selects a port if it wished to receive the cell that the port is holding. it does this by asserting rxen . the phy then transfers the data 16 bits each clock cycle, as determined by rxen . as in the transmit direction, the atm device may suspend transfer by deasserting rxen at any time. note that the phy asserts rxsoc coincident with the first 16 bits of each cell. txparity and rxparity are parity bits for the corresponding 16-bit data fields. odd parity is used. figures 8 through 13 may be referenced for utopia 2 bus examples. because this interface transfers an even number of bytes, rather than the atm standard of 53 bytes, a filler byte is inserted between the 5-byte header and the 48-byte payload. this is shown in figure 7. figure 7. utopia level 2 data format and sequence
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 17 figure 8. utopia 2 transmit handshake - back to back cells figure 9. utopia 2 transmit handshake - delay between cells txclk txsoc txclav txdata[15:0], txparity p43, 44 p45, 46 p47, 48 h1, 2 h3, 4 h5, undefined 3505 drw 10 txaddr[4:0] 1f n+3 1f n+2 1f n+3 1f n 1f n+3 n+2 n+3 n n+1 phy n phy n+3 cell transmission to: polling polling polling: selection p1, 2 high-z txclk txsoc txclav txdata[15:0], txparity p39, 40 p41, 42 p43, 44 p45, 46 p47, 48 h1, 2 h3, 4 h5, undefined 3505 drw 09 txaddr[4:0] 1f n+3 1f n+2 1f n+3 1f n 1f n+3 n+2 n+3 n n+1 phy n phy n+3 cell transmission to: polling polling polling: selection p1, 2 high-z
18 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges txclk txsoc txclav txdata[15:0], txparity p25, 26 p27, 28 p29, 30 p31, 32 p33, 34 3505 drw 11 txaddr[4:0] 1f n+3 1f n+2 1f m 1f n 1f n+3 n+2 m n n+1 phy m phy m cell transmission to: polling polling polling: selection p35, 36 high-z high-z high-z figure 10. utopia 2 transmit handshake - transmission suspended figure 11. utopia 2 receive handshake - back to back cells rxclk rxsoc rxclav rxdata[15:0], rxparity p39, 40 p41, 42 p43, 44 p45, 46 p47, 48 h1, 2 h3, 4 h5, undefined 3505 drw 12 rxaddr[4:0] 1f n+3 1f n+2 1f n+3 1f n 1f n+3 n+2 n+3 n n+1 phy n phy n+3 cell transmission to: polling polling polling: selection p1, 2 high-z high-z high-z
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 19 figure 12. utopia 2 receive handshake - delay between cells figure 13. utopia 2 receive handshake - suspended transfer of data rxclk rxsoc rxclav rxdata[15:0], rxparity p45, 46 p47, 48 h1, 2 h3, 4 3505 drw 13 rxaddr[4:0] n+3 1f n+2 1f n+1 1f n+1 1f n+3 n+2 n+1 n+1 n phy n+3 phy n+1 cell transmission to: polling polling polling: selection undefined 1f high-z high-z high-z rxclk rxsoc rxclav rxdata[15:0], rxparity p25, 26 p27, 28 p29, 30 p31, 32 p33, 34 3505 drw 14 rxaddr[4:0] n+3 1f n+2 1f m 1f n+1 1f n+3 n+2 m n+1 phy m phy m cell transmission from: polling polling polling: re-selection p35, 36 n+2 high-z high-z high-z
20 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges txclk txsoc txclav[2:0] [2:0] txdata[7:0], txparity x h1 h2 p44 p45 p46 p47 p48 x 4781 drw 16 figure 15. utopia 1 transmit handshake - single cell utopia level 1 multi-phy interface option the utopia level 1 multi-phy interface operates as defined in atm forum document af-phy-0017 and clarified in af-phy-0039. utopia level 1 is essentially the same as utopia level 2, but without the addressing, polling and selection features. instead of addressing, it utilizes separate txclav, txen , rxclav and rxen signals for each channel of the 77v1254. there are just one each of the txsoc and rxsoc signals, which are shared across all three channels. in addition to utopia level 2's cell mode transfer protocol, utopia level 1 also offers the option of a byte mode protocol. bit 1 of the master control registers is used to program whether the utopia level 1 bus is in cell mode or byte mode. in byte mode, the phy is allowed to control data transfer on a byte-by-byte basis via the txclav and rxclav signals. in cell mode, txclav and rxclav are ignored once the transfer of a cell has begun. in every other way the two modes are identical. cell mode is the default configuration and is the one described later. the utopia 1 signals are summarized below: txdata[7:0] atm to phy txparity atm to phy txsoc atm to phy txen [2:0] atm to phy txclav[2:0] phy to atm txclk atm to phy rxdata[7:0] phy to atm rxparity phy to atm rxsoc phy to atm rxen [2:0] atm to phy rxclav[2:0] phy to atm rxclk atm to phy transmit and receive both utilize free running clocks, which are inputs to the 77v1253. all utopia signals are timed to these clocks. in the transmit direction, the phy first asserts txclav (transmit cell available) to indicate that it has room in its header byte 1 header byte 3 header byte 5 payload byte 1 payload byte 3 header byte 2 header byte 4 payload byte 2 payload byte 46 payload byte 47 payload byte 48 bit 7 bit 0 3505 drw 15 first last figure 14. utopia 1 data format and sequence transmit fifo to accept at least one 53-byte atm cell. when the atm layer device is ready to begin passing the cell, it asserts txen (transmit enable) and txsoc (start of cell), coincident with the first byte of the cell on txdata. txen remains asserted for the duration of the cell transfer, but the atm device may deassert txen at any time once the cell transfer has begun, but data is transfered only when txen is asserted. in the receive direction, rxen indicates when the atm device is prepared to receive data. as with transmit, it may be asserted or deasserted at any time. the phy asserts rxclav to indicate that it has an entire cell to transfer. in both transmit and receive, txsoc and rxsoc (start of cell) is asserted for one clock, coincident with the first byte of each cell. odd parity is utilized across each 8-bit data field. figure 14 shows the data sequence for an atm cell over utopia level 1, and figures 15 to 21 are examples of the utopia level 1 handshake.
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 21 figure 18. utopia 1 receive handshake - delay between cells txclk txsoc txclav[2:0] [2:0] txdata[7:0], txparity p46 p47 p48 h1 h2 h3 h4 x h5 4781 drw 17 txclk txsoc txclav[2:0] [2:0] txdata[7:0], txparity p42 p43 p44 p45 p46 x x x p47 4781 drw 18 p48 h1 figure 16. utopia 1 transmit handshake - back-to-back cells, and txen txen txen txen txen suspended transmission figure 17. utopia 1 transmit handshake - txen txen txen txen txen suspended transmission and back-to-back cells (byte mode only) rxclk rxsoc rxclav[2:0] [2:0] rxdata[7:0], rxparity h1 h2 h3 4781 drw 19 p48 p47 high-z high-z
22 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 21. utopia 1 receive handshake - rxclav suspended transfer (byte mode only) figure 19. utopia 1 receive handshake - rxen rxen rxen rxen rxen and rxclav control figure 20. utopia 1 receive handshake - rxclav deassertion rxclk rxsoc rxclav[2:0] [2:0] rxdata[7:0], rxparity h1 p47 p48 4781 drw 20 p48 p47 high-z high-z x x h1 h2 rxclk rxsoc rxclav[2:0] [2:0] rxdata[7:0], rxparity p48 x 4781 drw 21 p44 p42 high-z high-z p43 p45 p46 p47 high-z high-z x early rxclav option (bit 6=1, registers 0x02, 0x12, 0x22) rxclk rxsoc rxclav[2:0] [2:0] rxdata[7:0], rxparity h1 h2 x 4781 drw 22 high-z high-z h3 h4 h5 p1
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 23 dpi interface option the dpi interface is relatively new and worth additional description. the biggest difference between the dpi configurations and the utopia configurations is that each channel has its own dpi interface. each interface has a 4-bit data path, a clock and a start-of-cell signal, for both the transmit direction and the receive direction. therefore, each signal is point-to-point, and none of these signals has high-z capability. additionally, there is one master dpi clock input (dpiclk) into the 77v1253 which is used as a source for the dpi transmit clock outputs. dpi is a cell-based transfer scheme like utopia level 2, whereas utopia level 1 transfers can be either byte- or cell-based. another unique aspect of dpi is that it is a symmetrical interface. it is as easy to connect two phys back-to-back as it is to connect a phy to a switch fabric chip. in contrast, utopia is asymmetrical. note that for the 77v1253, we are using the "transmit" and "receive" nomenclature in the naming of the dpi signals, whereas other devices may use more generic "in" and "out" nomenclature for their dpi signals. the dpi signals are summarized below, where "pn_" refers to the signals for channel number "n": dpiclk input to phy pn_tclk phy to atm pn_td[3:0] atm to phy pn_tfrm atm to phy pn_rclk atm to phy pn_rd[3:0] phy to atm pn_rfrm phy to atm in the transmit direction (atm to phy), the atm layer device asserts start-of-cell signal (pn_tfrm) for one clock cycle, one clock prior to driving the first nibble of the cell on pn_td[3:0]. once the atm side has begun sending a cell, it is prepared to send the entire cell without interruption. the 77v1253 drives the transmit dpi clocks (pn_tclk) back to the atm device, and can modulate (gap) it to control the flow of data. specifically, if it cannot accept another nibble, the 77v1253 disables pn_tclk and does not generate another rising edge until it has room for the nibble. pn_tclk are derived from the dpiclk free running clock source. header byte 1, (8:5) header byte 1, (4:1) header byte 2, (8:5) header byte 2, (4:1) header byte 3, (8:5) header byte 3, (4:1) header byte 4, (8:5) header byte 4, (4:1) header byte 5, (8:5) header byte 5, (4:1) payload byte 1, (8:5) payload byte 1, (4:1) payload byte 47, (8:5) payload byte 47, (4:1) payload byte 48, (8:5) payload byte 48, (4:1) bit 3 bit 0 3505 drw 23 first last figure 22. dpi data format and sequence the dpi protocol is exactly symmetrical in the receive direction, with the 77v1253 driving the data and start-of-cell signals while receiving pn_rclk as an input. the dpi data interface is four bits, so the 53 bytes of an atm cell are transferred in 106 cycles. figure 22 shows the sequence of that data transfer. figures 23 through 30 show how the handshake operates.
24 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges p_rfrm (out) p_rd(3:0) (out) x cell 1 nibble 0 x x 3505 drw 24 p_rclk (in) x cell 1 nibble 104 cell 1 nibble 105 p_rfrm (out) p_rd(3:0) (out) x cell 1 nibble 0 cell 1 nibble 1 cell 1 nibble 104 cell 1 nibble 105 cell 2 nibble 0 cell 2 nibble 1 3505 drw 25 p_rclk (in) x cell 1 p_rfrm (out) p_rd(3:0) (out) cell 2 nibble 0 cell 2 nibble 1 cell 2 nibble 2 cell 2 nibble 3 cell 2 nibble 4 3505 drw 26 p_rclk (in) cell 1 nibble 105 cell 1 nibble 104 figure 23. dpi receive handshake - one cell received figure 24. dpi receive handshake - back-to-back cells figure 25. dpi receive handshake - atm layer device suspends transfer
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 25 figure 28. dpi transmit handshake - back-to-back cells for transmission p_rfrm (out) p_rd(3:0) (out) xx x cell 2 nibble 0 cell 2 nibble 2 cell 2 nibble 1 3505 drw 27 p_rclk (in) x cell 1 nibble 104 cell 1 nibble 105 atm layer device not ready 77v1254 not ready p_tfrm (in) p_td(3:0) (in) x cell 1 nibble 0 x x 3505 drw 28 p_tclk (out) x cell 1 nibble 1 cell 1 nibble 104 cell 1 nibble 105 p_tfrm (in) p_td(3:0) (in) x cell 1 nibble 0 cell 1 nibble 1 cell 1 nibble 104 cell 1 nibble 105 cell 2 nibble 0 cell 2 nibble 1 3505 drw 29 p_tclk (out) x cell 1 figure 26. dpi receive handshake - neither device ready figure 27. dpi transmit handshake - one cell for transmission
26 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 30. dpi transmit handshake - neither device ready figure 29. dpi transmit handshake - 77v1254 transmit fifo full p_tfrm (in) p_td(3:0) (in) cell 2 nibble 0 cell 2 nibble 1 cell 2 nibble 2 cell 2 nibble 3 cell 2 nibble 4 3505 drw 30 p_tclk (out) cell 1 nibble 105 cell 1 nibble 104 p_tfrm (in) p_td(3:0) (in) xx x cell 2 nibble 0 cell 2 nibble 2 cell 2 nibble 1 3505 drw 31 p_tclk (out) x cell 1 nibble 104 cell 1 nibble 105 77v1254 not ready atm layer device not ready
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 27 figure 31. rxled(2:0) txled(2:0) 3.3v (indicates: cells being received or transmitted) (indicates: cells are not being received or transmitted) 3505 drw 32 r r control and status interface utility bus the utility bus is a byte-wide interface that provides access to the registers within the IDT77V1253. these registers are used to select desired operating characteristics and func- tions, and to communicate status to external systems. the utility bus is implemented using a multiplexed address and data bus (ad[7:0]) where the register address is latched via the address latch enable (ale) signal. the utility bus interface is comprised of the following pins: ad[7:0], ale, cs , rd , wr read operation refer to the utility bus timing waveforms in figures 42 - 43. a register read is performed as follows: 1. initial condition: - rd , wr , cs not asserted (logic 1) - ale not asserted (logic 0) 2. set up register address: - place desired register address on ad[7:0] - set ale to logic 1; - latch this address by setting ale to logic 0. 3. read register data: - remove register address data from ad[7:0] - assert cs by setting to logic 0; - assert rd by setting to logic 0 - wait minimum pulse width time (see ac speci- fications) write operation a register write is performed as described below: 1. initial condition: - rd , wr , cs not asserted (logic 1) - ale not asserted (logic 0) 2. set up register address: - place desired register address on ad[7:0] - set ale to logic 1; - latch this address by setting ale to logic 0. 3. write data: - place data on ad[7:0] - assert cs by setting to logic 0; - assert wr (logic 0) for minimum time (according to timing specification); reset wr to logic 1 to complete register write cycle. interrupt operations the IDT77V1253 provides a variety of selectable interrupt and signalling conditions which are useful both during nor- mal operation, and as diagnostic aids. refer to the status and control register list section. overall interrupt control is provided via bit 0 of the master control registers. when this bit is cleared (set to 0), interrupt signalling is prevented on the respective port. the interrupt mask registers allow individual masking of different interrupt sources. additional interrupt signal control is provided by bit 5 of the master control registers. when this bit is set (=1), receive cell errors will be flagged via interrupt signalling and all other interrupt conditions are masked. these errors in- clude: - bad receive hec - short (fewer than 53 bytes) cells - received cell symbol error normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the master control registers. int (pin 85) will go to a low state when an interrupt condition is detected. the external system should then interrogate the 77v1253 to determine which one (or more) conditions caused this flag, and reset the interrupt for further occurrences. this is accom- plished by reading the interrupt status registers. decoding the bits in these bytes will tell which error condition caused the interrupt. reading these registers also: - clears the (sticky) interrupt status bits in the registers that are read - resets int this leaves the interrupt system ready to signal an alarm for further problems. led control and signalling the led outputs provide bi-directional led drive capability of 8 ma. as an example, the rxled outputs are described in the truth table: state pin voltage cells being received low cells not being received high as illustrated in the following drawing (figure 31), this could be connected to provide for a two-led condition indicator. these could also be different colors to provide simple status indication at a glance. (the minimum value for r should be 330 w , but a value closer to 1 k w is recommended). txled truth table state pin voltage cells being transmitted low cells not being transmitted high
28 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 32. normal mode figure 33. phy loopback atm layer device tc sublayer pmd sublayer line interface 4781 drw 34 IDT77V1253 tc sublayer pmd sublayer line interface atm layer device 4781 drw 33 IDT77V1253 diagnostic functions 1. loopback there are two loopback modes supported by the 77v1253. the loopback mode is controlled via bits 1 and 0 of the diagnostic control registers: bit 1 bit 0 mode 0 0 normal operating mode 1 0 phy loopback 1 1 line loopback normal mode this mode, figure 32, supports normal operating condi- tions: data to be transmitted is transferred to the tc, where it is queued and formatted for transmission by the pmd. re- ceive data from the pmd is decoded along with its clock for transfer to the receiving "upstream system". phy loopback as figure 33 illustrates below, this loopback mode pro- vides a connection within the phy from the transmit phy- atm interface to the phy-atm receive interface. note that while this mode is operating, no data is forwarded to or received from the line interface. line loopback figure 34 might also be called remote loopback since it provides for a means to test the overall system, including the line. since this mode will probably be entered under direction from another system (at a remote location), receive data is also decoded and transferred to the upstream system to allow it to listen for commands. a common example would be a command asking the upstream system to direct the tc to leave this loopback state, and resume normal operations.
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 29 2. counters several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions. it is anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. a separate set of registers exists for each channel of the phy. ? symbol error counters - 8 bits - counts all invalid 5-bit symbols received ? transmit cell counters - 16 bits - counts all transmitted cells ? receive cell counters - 16 bits - counts all received cells, excluding idle cells and hec errored cells ? receive hec error counters - 5 bits - counts all hec errors received the txcell and rxcell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. the symbol error counter and hec error counter were given sufficient size to indicate exact counts for low error-rate conditions. if these counters overflow, a gross condition is occurring, where additional counter resolution does not provide additional diagnostic benefit. reading counters 1. decide which counter value is desired. write to the counter select register(s) (0x06, 0x16 and 0x26) to the bit location corresponding to the desired counter. this loads the high and low byte counter registers with the selected counters value, and resets this counter to zero. note: only one counter may be enabled at any time in each of the counter select registers. 2. read the counter registers (0x04, 0x14 or 0x24 (low byte)) and (0x05, 0x15 or 0x25 (high byte)) to get the value. further reads may be accomplished in the same manner by writing to the counter select registers. vpi/vci swapping for compatibility with idt's switchstar products (77v400 and 77v500), the 77v1253 has the ability to swap parts of the vpi/vci address space in the header of receive cells. this function is controlled by the vpi/vci swap bits, which are bit 5 of the enhanced control registers (0x08, 0x18 and 0x28). the portions of the vpi/vci that are swapped are shown below. bits x(7:0) are swapped with y(7:0) when the vpi/vci swap bit is set and the chip is in dpi mode. figure 34. line loopback atm layer device tc sublayer pmd sublayer line interface 4781 drw 35 IDT77V1253 byte 0 byte 1 byte 2 byte 3 byte 4 0 7 gfc/vpi vpi vci pti hec vci vci vpi byte 0 byte 1 byte 2 byte 3 byte 4 0 7 clp x7 x6 x5 x4 x3 x2 x1 x0 y3 y2 y1 y0 y7 y6 y5 y4 3505 drw 51
30 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 35. recommended connection to magnetics 7 8 10 9 3 4 5 magnetics rj45 connector IDT77V1253 idt77v1254 agnd 14 13 12 agnd 1 2 16 15 agnd avdd rxd+ rxd- txd+ txd- r1 r2 r3 r4 r5 r8 r9 r7 c1 c2 l1 3505 drw 36 r6 1 2 3 4 5 6 7 8 table 3 analog component values component value tolerance r1 47 w 5% r2 47 w 5% r3 620 w 5% r4 110 w 5% r5 2700 w 5% r6 2700 w 5% r7 82 w 5% r8 33 w 5% r9 33 w 5% c1 470pf 20% c2 470pf 20% l1 3.3 m h 20% magnetics modules for 25.6 mbps pulse pe-67583 or r4005 (619) 674-8100 tdk tla-6m103 (847) 803-6100 valor sf1153 (800) 318-2567 magnetics modules for 51.2 mbps pulse r4005 (619) 674-8100 line side (serial) interface each of the four ports has two pins for differential serial transmission, and two pins for differential serial receiving. phy to magnetics interface a standard connection to 100 w and 120 w unshielded twisted pair cabling is shown in figure 35. note that the transmit signal is somewhat attenuated in order to meet the launch amplitude specified by the standards. the receive circuitry is designed to attenuate low frequencies in order to compensate for the high frequency attenuation of the cable. also, the receive circuitry biases the positive and negative rx inputs to slightly different voltages. this is done so that the receiver does not receive false signals in the absence of a real signal. this can be important because the 77v1253 does not disable error detection or interrupts when an input signal is not present. when connecting to utp at 51.2 mbps, it is necessary to use magnetics with sufficient bandwidth. such a device can also operate satisfactorily at 25.6 mbps.
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 31 nomenclature "reserved" register bits, if written, should always be written "0" r/w = register may be read and written via the utility bus r-only or w-only = register is read-only or write-only sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only 0 = cleared or not set 1 = set master control registers addresses: 0x00, 0x10, 0x20 bit type initial state function 7 r/w 0 reserved 6 r/w 1 = discard discard receive error cells errored cells on receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive hec error (if enabled)), this cell will be discarded and will not enter the receive fifo. 5 r/w 0 = all interrupts enable cell error interrupts only if bit 0 in this register is set (interrupts enabled), setting of this bit enables only received cell error (as defined in bit 6) to trigger interrupt line. 4 r/w 0 = disabled transmit data parity check directs tc to check parity of txdata against parity bit located in txparity. 3 r/w 1 = discard discard received idle cells idle cells directs tc to discard received idle (vpi/vci = 0) cells from pmd without signaling external systems. 2 r/w 0 = not halted halt tx halts transmission of data from tc to pmd and forces both txd signals low. 1 r/w 0 = cell mode utopia level 1 mode select: 0 = cell mode, 1 = byte mode. not applicable for utopia 2 or dpi modes. 0 r/w 1 = enable enable interrupt pin (interrupt mask bit) interrupts enables interrupt output pin (pin 85). if cleared, pin is always high and interrupt is masked. if set, an interrupt will be signaled by setting the interrupt pin to 0. status and control register list the 77v1253 has 28 registers that are accessible through the utility bus. each of the three ports has 9 registers dedicated to that port. there is only one register (0x40) which is not port specific. for those register bits which control operation of the utopia interface, the operation of the utopia interface is determined by the registers corresponding to the port which is selected at that particular time. for consistent operation, the utopia control bi ts should be programmed the same for all three ports, except for the utopia 2 port addresses in the enhanced control registers. register address register name port 0 port 1 port 2 all ports master control registers 0x00 0x10 0x20 interrupt status registers 0x01 0x11 0x21 diagnostic control registers 0x02 0x12 0x22 led driver and hec status/control 0x03 0x13 0x23 low byte counter register [7:0] 0x04 0x14 0x24 high byte counter register [15:8] 0x05 0x15 0x25 counter registers read select 0x06 0x16 0x26 interrupt mask registers 0x07 0x17 0x27 enhanced control registers 0x08 0x18 0x28 rxref and txref control register 0x40
32 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges interrupt status registers addresses: 0x01, 0x11, 0x21 bit type initial state function 7 reserved 6 r 0 = bad signal good signal bit see definitions on pages 14 and 15 1 = good signal 0 = bad signal 5 sticky 0 hec error cell received set when a hec error is detected on a received cell. 4 sticky 0 short cell received interrupt signal which flags received cells with fewer than 53 bytes. this condition is detected when receiving start-of-cell command bytes with fewer than 53 bytes between them. 3 sticky 0 transmit parity error if bit 4 of register 0x00 / 0x10 / 0x20 is set (transmit data parity check), this interrupt flags a transmit data parity error condition. odd parity is used. 2 sticky 0 receive signal condition change this interrupt is set when the received signal changes either from bad to good or from good to bad. 1 sticky 0 received symbol error set when an undefined 5-bit symbol is received. 0 sticky 0 receive fifo overflow interrupt which indicates when the receive fifo has filled and cannot accept additional data. diagnostic control registers addresses: 0x02, 0x12, 0x22 bit type initial state function 7 r/w 0=normal force txclav deassert (applicable only in utopia 1 and 2 modes) used during line loopback mode to prevent upstream system from continuing to send data to the 77v1253. not applicable in dpi mode. 6 r/w 0=utopia rxclav operation select (for utopia 1 mode) the utopia standard dictates that during cell mode operation, if the receive fifo no longer has a complete cell available for transfer from phy, rxclav is deasserted following transfer of the last byte out of the phy to the upsteam system. with this bit set, early deassertion of this signal will occur coincident with the end of payload byte 44 (as in octet mode for txclav). this provides early indication to the upstream system of this impending condition. 0 = standard utopia rxclav 1 = cell mode = byte mode 5 r/w 1 = tri-state single/multi-phy configuration select (applicable and writable only in utopia 1 mode) 0 = single: never tri-state rxdata, rxparity and rxsoc 1 = multi-phy mode: tri-state rxdata, rxparity and rxsoc when rxen = 1 4 r/w 0=normal rflush = clear receive fifo this signal is used to tell the tc to flush (clear) all data in the receive fifo. the tc signals this completion by clearing this bit. 3 r/w 0=normal insert transmit payload error tells tc to insert cell payload errors in transmitted cells. this can be used to test error detection and recovery systems at destination station, or, under loopback control, at the local receiving station. this payoad error is accomplished by flipping bit 0 of the last cell payload byte. 2 r/w 0=normal insert transmit hec error tells tc to insert hec error in byte 5 of cell. this can be used to test error detection and recovery systems in down-stream switches, or, under loopback control, the local receiving station. this hec error is accomplilshed by flipping bit 0 of the hec byte. 1,0 r/w 00=normal loopback control bit# 1 0 0 0 normal mode (receive from network) 1 0 phy loopback 1 1 line loopback
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 33 high byte counter registers [15:8] addresses: 0x05, 0x15, 0x25 bit type initial state function [7:0] r 0x00 provides high-byte of counter value selected via register 0x06, 0x16, 0x26 and 0x36. counter select registers addresses: 0x06, 0x16, 0x26 bit type initial state function 7 reserved 6 reserved 5 reserved 4 reserved 3 w 0 symbol error counter 2 w 0 txcell counter 1 w 0 rxcell counter 0 w 0 receive hec error counter note: only one bit may set at any time for proper operation low byte counter registers [7:0] addresses: 0x04, 0x14, 0x24 bit type initial state function [7:0] r 0x00 provides low-byte of counter value selected via registers 0x06, 0x16, 0x26 and 0x36. led driver and hec status/control registers addresses: 0x03, 0x13, 0x23 bit type initial state function 7 0 reserved 6 r/w 0 = enable checking disable receive hec checking (hec enable) when not set, the hec is calculated on first 4 bytes of received cell, and compared against the 5th byte. when set ( = 1), the hec byte is not checked. 5 r/w 0 = enable calculate & replace disable xmit hec calculate & replace when set, the 5th header byte of cells queued for transmit is not replaced with the hec calculated across the first four bytes of that cell. 4,3 r/w 00 = 1 cycle rxref rxref rxref rxref rxref pulse width select bit # 4 3 0 0 rxref active for 1 osc cycle 0 1 rxref active for 2 osc cycles 1 0 rxref active for 4 osc cycles 1 1 rxref active for 8 osc cycles 2 r 1 = empty fifo status 1=txfifo empty 0=txfifo not empty 1r0 txled status 1=cell received 0=cell not received 0r0 rxled status 1=cell received 0=cell not received
34 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges enhanced control registers addresses: 0x08, 0x18, 0x28 bit type initial state function 7 r/w 0 = not reset individual port software reset 1 = reset. this bit is not self clearing; must write 0 to exit reset. 6 r/w 0 = osc transmit line clock (or loop timing mode) when set to 0, the osc input is used as the transmit line clock. when set to 1, the recovered receive clock is used as the transmit line clock. 5 r/w 0 = no swap vpi/vci swap dpi mode only. receive direction only. see description on page 29. 4-0 r/w port 0 (reg 0x08): 00000 utopia 2 port address port 1 (reg 0x18): 00001 when operating in utopia 2 mode, these register bits determine the utopia 2 port 2 (reg 0x28): 00010 port addresses. interrupt mask registers addresses: 0x07, 0x17, 0x27 bit type initial state function 7 0 reserved 6 0 reserved 5 r/w 0 = interrupt enabled hec error cell 4 r/w 0 = interrupt enabled short cell error 3 r/w 0 = interrupt enabled transmit parity error 2 r/w 0 = interrupt enabled receive signal condition change 1 r/w 0 = interrupt enabled received cell symbol error 0 r/w 0 = interrupt enabled receive fifo overflow note: when set to "1", these bits mask the corresponding interrupts going to the interrupt pin ( int ). when set to "0", the interrupts are unmasked. these interrupts correspond to the interrupt status bits in the interrupt status registers. rxref rxref rxref rxref rxref and txref txref txref txref txref control register address: 0x40 bit type initial state function 7, 6 r/w 00 = rxref0 (port 0) rxref rxref rxref rxref rxref source select selects which of the three ports (0 to 2) is the source of rxref . 5 r/w 0 = not reset master software reset 1 = reset. this bit is not self clearing; must write 0 to exit reset. 4-3 0 reserved 2-0 r/w 0000 = not looped rxref rxref rxref rxref rxref to txref txref txref txref txref loop select when set to 0, txref is used to generate x_8 timing marker commands. when set to 1, txref input is ignored, and received x_8 timing commands are looped back and added to the transmit stream of that same port. see figure 6. bit 2: port 2 bit 1: port 1 bit 0: port 0
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 35 symbol parameter test conditions min. max unit i li input leakage current gnd v in v dd C5 5 m a i lo i/o (as input) leakage current gnd v in v dd C10 10 m a v oh1 (1) output logic 1 voltage i oh = C2 ma, v dd = min. 2.4 v v oh2 (2) output logic 1 voltage i oh = C8 ma, v dd = min. 2.4 v v ol (3) output logic 0 voltage i ol = 8 ma, v dd = min. 0.4 v i dd1 (4, 5) digital power supply current - vdd osc = 32 mhz, all outputs unloaded 140 ma i dd2 (5) analog power supply current - avdd osc = 32 mhz, all outputs unloaded 140 ma notes: 1. for ad[7:0] pins only. 2. for all output pins except ad[7:0], int and tx+/-. 3. for all output pins except tx+/-. 4. add 15ma for each tx+/- pair that is driving a load 5. total supply current is the sum of i dd1 and i dd2 . notes: 3139 tbl 05 1. characterized values, not currently tested. symbol parameter conditions max. unit c in (1) input vin = 0v 10 pf capacitance c io (1) i/o vout = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1mhz) recommended dc operating conditions symbol parameter min. typ. max. unit vdd digital supply voltage 3.0 3.3 3.6 v gnd digital ground voltage 0 0 0 v vih input high voltage 2.0 5.25 v vil input low voltage -0.3 0.8 v avdd analog supply voltage 3.0 3.3 3.6 v agnd analog ground voltage 0 0 0 v vdif vdd - avdd -0.5 0 0.5 v absolute maximum ratings (1) symbol rating value unit v term terminal voltage C0.5 to +5.5 v with respect to gnd t bias temperature under C55 to +125 c bias t stg storage C55 to +125 c temperature i out dc output current 50 ma note: 3139 tbl 02 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty. dc electrical characteristics (all pins except tx+/- and rx+/-) grade ambient gnd, agnd vdd, avdd temperature commercial 0 c to 70 c 0v 3.3v 0.3v industrial -40 c to +85 c 0v 3.3v 0.3v recommended operating temperature and supply voltage symbol parameter test conditions min. max unit v oh1 output logic 1 voltage i oh = C20 ma vdd - 0.5v v v ol output logic 0 voltage i ol = 20 ma 0.5 v dc electrical characteristics (tx+/- output pins only)
36 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges symbol parameter min. max. units t1 txclk fequency 0.2 50 mhz t2 txclk duty cycle (% of t1) 40 60 % t3 txdata[15:0], txparity setup time to txclk 7 ns t4 txdata[15:0], txparity hold time totxclk 2 ns t5 txaddr[4:0] setup time to txclk 7 ns t6 txaddr[4:0] hold time to txclk 2 ns t7 txsoc, txen setup time to txclk 7 ns t8 txsoc, txen hold time to txclk 2 ns t9 txclk to txclav high-z 2 10 ns t10 txclk to txclav low-z (min) and valid (max) 2 14 ns t12 rxclk fequency 0.2 50 mhz t13 rxclk duty cycle (% of t12) 40 60 % t14 rxen setup time to rxclk 7 ns t15 rxen hold time to rxclk 2 ns t16 rxaddr[4:0] setup time to rxclk 7 ns t17 rxaddr[4:0] hold time to rxclk 2 ns t18 rxclk to rxclav high-z 2 14 ns t19 rxclk to rxclav low-z (min) and valid (max) 2 10 ns t20 rxclk to rxsoc high-z 2 10 ns t21 rxclk to rxsoc low-z (min) and valid (max) 2 14 ns t22 rxclk to rxdata, rxparity high-z 2 10 ns t23 rxclk to rxdata, rxparity low-z (min) and valid (max) 2 14 ns utopia level 2 bus timing parameters figure 36. utopia level 2 transmit 3505 drw 37 txclav txdata[15:0], txparity txaddr[4:0] txsoc txclk t 3 t 10 t 7 t 4 t 1 t 2 t 9 t 10 high-z high-z t 8 t 5 t 6 octet 1 octet 2
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 37 symbol parameter min. max. units t31 txclk fequency 0.2 50 mhz t32 txclk duty cycle (% of t31) 40 60 % t33 txdata[7:0], txparity setup time to txclk 7 ns t34 txdata[7:0], txparity hold time totxclk 2 ns t35 txsoc, txen [3:0] setup time to txclk 7 ns t36 txsoc, txen [3:0] hold time totxclk 2 ns t37 txclk to txclav[3:0] invalid (min) and valid (max) 2 14 ns t39 rxclk fequency 0.2 50 mhz t40 rxclk duty cycle (% of t39) 40 60 % t41 rxen [3:0] setup time to rxclk 7 ns t42 rxen [3:0] hold time to rxclk 2 ns t43 rxclk to rxclav[3:0] invalid (min) and valid (max) 2 14 ns t44 rxclk to rxsoc high-z 2 10 ns t45 rxclk to rxsoc low-z (min) and valid (max) 2 14 ns t46 rxclk to rxdata, rxparity high-z 2 10 ns t47 rxclk to rxdata, rxparity low-z (min) and valid (max) 2 14 ns utopia level 1 bus timing parameters figure 37. utopia level 2 receive 3505 drw 38 rxclav rxdata[15:0], rxparity rxaddr[4:0] rxsoc rxclk t 19 t 14 t 12 t 13 t 18 t 19 high-z high-z t 15 t 16 t 17 t 21 t 23 t 22 t 20 t 23 t 21 high-z high-z high-z high-z
38 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges figure 39. utopia level 1 receive 4781 drw 40 rxclav[2:0] rxdata[7:0], rxparity rxsoc rxclk t 41 t 39 t 40 t 43 t 42 t 45 t 47 t 46 t 44 t 47 t 45 high-z high-z high-z high-z figure 38. utopia level 1 transmit 4781 drw 39 txclav[2:0] txdata[7:0], txparity txsoc txclk t 33 t 37 t 35 t 34 t 31 t 32 t 36 octet 1 octet 2
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 39 symbol parameter min. max. units t51 dpiclk frequency 0.2 40 mhz t52 dpiclk duty cycle (% of t51) 40 60 % t53 dpiclk to pn_tclk propagation delay 2 14 ns t54 pn_tfrm setup time to pn_tclk 11 ns t55 pn_tfrm hold time to pn_tclk 1 ns t56 pn_td[3:0] setup time to pn_tclk 11 ns t57 pn_td[3:0] hold time to pn_tclk 1 ns t61 pn_rclk period 25 ns t62 pn_rclk high time 10 ns t63 pn_rclk low time 10 ns t64 pn_rclk to pn_rfrm invalid (min) and valid (max) 2 12 ns t65 pn_rclk to pn_rd invalid (min) and valid (max) 2 12 ns dpi bus timing parameters figure 41. dpi receive 3505 drw 41 pn_td[3:0] pn_tclk pn_tfrm dpiclk t 54 t 51 t 52 t 55 t 53 t 56 t 57 3505 drw 42 pn_rd[3:0] pn_rclk pn_rfrm t 61 t 62 t 64 t 65 t 63 figure 40. dpi transmit
40 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 3505 drw 44 ale ad[7:0] tah tas tapw tch tdwh tdws twrpw address data (input) taw tcswr utility bus read cycle name min max unit description tas 10 ns address setup to ale tcsrd 0 ns chip select to read enable tah 5 ns address hold to ale tapw 10 ns ale min pulse width ttria 0 ns address tri-state to rd assert trdpw 20 ns min. rd pulse width tdh 0 ns data valid hold time tch 0 ns rd deassert to cs deassert ttrid 10 ns rd deassert to data tri-state trd 5 18 ns read data access tar 5 ns ale low to start of read trdd 0 ns start of read to data low-z utility bus write cycle name min max unit description tapw 10 ns ale min pulse width tas 10 ns address set up to ale tah 5 ns address hold time to ale tcswr 0 ns cs assert to wr twrpw 20 ns min. wr pulse width tdws 20 ns write data set up tdwh 10 ns write data hold time tch 0 ns wr deassert to cs deassert taw 20 ns ale low to end of write 3505 drw 43 ale tah tas tapw tch trdd trdpw ad[7:0] (output) tdh trd ttrid tcsrd address data tar ad[7:0] (input) figure 43. utility bus write cycle figure 42. utility bus read cycle
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 41 figure 44. osc, rxref rxref rxref rxref rxref , txref txref txref txref txref and reset timing figure 45. output load * includes jig and scope capacitances. ac test conditions input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 45 30pf* 1.2k w 3.3v 900 w d.u.t. 3505 drw 46 3505 drw 45 osc trrpd trspw ttrl trrpd ttrh tcyc tch tcl notes: 1. the width of the rxref pulse is programmable in the led driver and hec status/control registers. 2. the minimum reset pulse width is either two rxclk cycles, two txclk cycles, two dpiclk cycles or two osc cycles, whichever is greater (and applicable). symbol parameter min. typ. max. unit tcyc osc cycle period (25.6 mbps) 30 31.25 33 ns (51.2 mbps) 15 15.625 16.5 ns tch osc high time 40 60 % tcl osc low time 40 60 % tcc osc cycle to cycle period variation 1 % trrpd (1) osc to rxref propagation delay 1 30 ns ttrh txref high time 35 ns ttrl txref low time 35 ns trspw (2) minimum rst pulse width two txclk cycles two rxclk cycles two dpiclk cycles two osc cycles osc, rxref rxref rxref rxref rxref , txref txref txref txref txref and reset timing
42 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges magnetics 1 2 3 4 5 6 7 8 9 10111213141516 rj45 connector 1 2 7 8 agnd tx2+ tx2- idt 77v1253 note 1 note 2 rx filter tx filter 4781 drw 47 rx tx 110 109 141 142 112 111 agnd rj45 magnetics rj45 magnetics 120 121 rx2+ rx2- note 3 magnetics 1 2 3 4 5 6 7 8 9 10111213141516 rj45 connector 1 2 7 8 agnd tx2+ tx2- idt 77v1253 note 1 note 2 tx filter rx filter 4781 drw 48 tx rx 110 109 141 142 112 111 agnd rj45 magnetics rj45 magnetics 120 121 rx2+ rx2- note 3 figure 46. pc board layout for atm network figure 47. pc board layout for atm user notes: 1. no power or ground plane inside this area. 2. analog power plane inside this area. 3. digital power plane inside this area. 4. a single ground plane should extend over the area covered by the analog and digital power planes, without breaks. 5. all analog signal traces should avoid 90 corners. notes: 1. no power or ground plane inside this area. 2. analog power plane inside this area. 3. digital power plane inside this area. 4. a single ground plane should extend over the area covered by the analog and digital power planes, without breaks. 5. all analog signal traces should avoid 90 corners. a note about figures 46 and 47: the atm forum and itu-t standards for 25 mbps atm define "network" and "user" interfaces. they are identical except that transmit and receive are switched between the two. a network device can be connected directly to a user device with a straight-through cable. user-to-user or network-to-network connections require a cable with 1-to-7 and 2-to-8 crossovers.
IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges 43 package dimensions 2'-6" 1 144 a1 a2 e b 144-pin pqfp l 5'-6" d 4'-5" d1 a 4'-4" 5'-5" e1 e a a1 a2 d d1 e e1 l e b - 0.25 3.20 - - - - 0.73 - 0.22 3.70 0.33 3.37 31.20 28.00 31.20 28.00 0.88 0.65 - 4.07 - 3.60 - - - - 1.03 - 0.38 symbol min. nom. max. dimensions are in millimeters 37 36 72 73 108 109 3505 drw 49
44 IDT77V1253 preliminary 25.6 and 51.2 mbps atm triple phy commercial and industrial temperature ranges integrated device technology, inc. 2975 stender way, santa clara, ca 95054-3090 telephone: (408) 727-6116 fax 408-492-8674 integrated device technology, inc. reserves the right to make changes to the specifications in this data sheet in order to impr ove design or performance and to supply the best possible product. ordering information preliminary datasheet: definition "preliminary" datasheets contain descriptions for products soon to be, or recently, released to production, including features, pinouts and block diagrams. timing data are based on simulation or initial characterization and are subject to chang e upon full characterization. datasheet document history 11/30/98: preliminary. initial draft. package idt nnnnn device type a power nnn speed a a process/ temp. range blank 25 speed in mb/s 77v1253 triple 25mb/s atm phy transmission convergence (tc) and pmd sublayers commercial (0 c to +70 c) 4781 drw 50 l pg 144-pin pqfp i industrial (-40 c to +85 c)

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